Typical television video standards include NTSC, PAL, and SECAM. The NTSC standard has been adopted in, for example, the United States and Japan. The NTSC standard provides for an interlaced image with an image resolution of 640.times.480 pixels, or 320.times.240 pixels. An "interlaced" image is one where the odd and even horizontal lines of the image are updated on alternate frame refresh cycles. The odd and even fields are updated at about 30 hertz (Hz), and the image is, as a whole, is fully updated at a rate of about 60 Hz, which corresponds to the alternating current (AC) power supply cycle in the U.S. and Japan. Further, the data stream that carries the interlaced image is fed to a video display, such as a television monitor, via a pixel, or dot, clock operating at about 27 megahertz (MHz).
The PAL and SECAM video standards have been adopted other places in the world, including for example, Europe. The PAL/SECAM television video standards provide for an interlaced image with a typical resolution of 768.times.565, or 384.times.283 pixels. The odd and even fields are updated at about 25 Hz, and the image, as a whole, is fully updated at a rate of about 50 Hz, which corresponds to the AC power supply cycle in these countries. Moreover, the data stream is fed to a video display via a pixel clock operating at about 27 MHz.
In contrast to the NTSC, PAL, and SECAM video standards, a typical computer generated image is noninterlaced, can have a much higher resolution, and is usually generated by a data stream having a much higher frequency, or pixel (dot) clock. As an example, a typical resolution is 1280.times.1024 pixels, and a common pixel clock operates at about 135 MHz, which is more than four times that of the usual interlaced video pixel clocks.
It is oftentimes desirable to produce an interlaced video signal from a noninterlaced computer graphics signal. More specifically, engineering designs, particularly, animated designs, are often produced on workstations or high end computers that generate high resolution, high frequency, noninterlaced computer graphics signals for driving a computer graphics display. Further, it may be desirable to show the animated design on a low cost conventional video cassette recorder (VCR) or other device that utilizes the NTSC, PAL, or SECAM video standard. In order to accomplish this functionality, several approaches have been utilized.
One approach, called the Folsom technique or the Lyon-Lamb technique, involves capturing the computer generated analog signal passing from a graphics system to the computer graphics display. This technique is shown in FIG. 1A and generally denoted by reference numeral 11. With reference to FIG. 1, the system 11 includes a central processing unit (CPU) 12 interconnected as indicated by reference arrow 13 with a graphics system 14, which is in turn interconnected with a computer display 16. The graphics system 14 drives a high resolution, high frequency, noninterlaced analog signal to the computer display 16, as indicated by reference arrows 15, 15a. In accordance with the Folsom or Lyon-Lamb technique, a video processing system 18 is interconnected with the graphics system 14 to receive the analog noninterlaced video signal, as indicated by reference arrows 15, 15b. The video processing system 18 includes, among other things, an analog-to-digital converter (ADC), a frame buffer, and a processor for controlling the foregoing elements in order to generate a low resolution, low frequency, interlaced video signal 21. Although meritorious to an extent, this system 11 is expensive as the video processing system 18 must deal with a high frequency analog signal. Further, there is degradation in data in that the source data is transformed from digital to analog and then back to digital again.
Another approach involves capturing a digitized noninterlaced graphics signal directly from the CPU, prior to processing by the computer's graphics system. This technique is illustrated in FIG. 1B and generally denoted by reference numeral 31. Referring to FIG. 1B, a video processing system 33, for example, an EISA video out card, is interconnected to the CPU 12, as indicated by reference arrow 13b in order to capture the high resolution, high frequency, noninterlaced graphics signal. The video processing system 33 includes, among other things, a frame buffer and processor, which in combination produce the low resolution, low frequency, interlaced video signal 21.
This approach has little merit in that the video processing system 33 cannot take advantage of the accelerators that are typically employed in the graphics system 14. Accelerators are used to implement, for example, translation, rotation, shading, texture mapping, etc. Furthermore, the video processing system 33 cannot acquire the contents of the frame buffer in the graphics system 14 in real time, i.e., in a fast enough time to generate the video signal 21. One reason is that typical graphics system 14 are designed so that data can be written fast to the graphics system 14, but read very slow from the graphics system 14. Moreover, such a transfer would require at least one iteration of write and read operations, which would obviously slow the transfer.
Another problem associated with the aforementioned approaches involves a phenomenon known as "flickering" in the generated interlaced video signal. When an interlaced image is created from a noninterlaced graphics signal, the interlaced image is oftentimes characterized by pixels that appear to strobe, or flicker. This predicament results from low resolution details being visible in an odd field, but not the even field, or vice versa. An example would include a single horizontal line disposed on an even line. In this example, the line would be generated during even field production, but not during odd field production. Thus, the high intensity data would appear to flicker.